Internal voltage generator

ABSTRACT

An internal voltage generator for stably generating an internal voltage includes a latch unit for outputting a first and a second driving signals based on a periodic signal; a first pump block for generating the internal voltage in response to the first driving signal; and a second pump block for generating the internal voltage in response to the second driving signal.

FIELD OF THE INVENTION

The present invention relates to an internal voltage generator; and,more particularly, to an internal voltage generator for stablymaintaining an internal voltage level having a short response time.

DESCRIPTION OF RELATED ARTS

Generally, an internal voltage generator included in a semiconductormemory device generates various voltages used in the semiconductormemory device by using an external power supply voltage. Recently, theinternal voltage generator is widely used in a dynamic random accessmemory (DRAM) as an operational voltage and a power consumption of theDRAM are decreased.

Meanwhile, since the internal voltage is internally generated, it isimportant to stably generate the internal voltage regardless ofvariations of process, temperature or pressure.

FIG. 1 is a block diagram showing a conventional internal voltagegenerator.

As shown, the conventional internal voltage generator includes a chargepumping unit 40 for generating an internal voltage VBB by performing anegative pumping operation to an external power supply voltage VDD; alevel detector 10 for detecting a voltage level of the internal voltageVBB to thereby generate a detection signal BBE; an oscillator 20 forgenerating a periodic signal OSC in response to the detection signalBBE; and a pumping control signal generator 30 for controlling anoperation of the charge pumping unit 40 according to the periodic signalOSC. Herein, a voltage level of the internal voltage VBB is lower thanthat of the external power supply voltage VDD.

When the voltage level of the internal voltage VBB is higher than apredetermined voltage level, the level detector 10 operates the chargepumping unit 40 through the oscillator 20 and the pumping control signalgeneration unit 30 in order to decrease the voltage level of theinternal voltage VBB to the predetermined voltage level. In this manner,the internal voltage VBB can have a constant voltage level.

Meanwhile, the charge pumping unit 40 can be embodied with adoubler-typed charge pump.

FIG. 2 is a schematic circuit diagram depicting the level detector 10shown in FIG. 1.

As shown, the level detector 10 includes a voltage divider 12, a firstinverter I1, a second inverter I2, a differential amplifier 14 and athird inverter I3.

The voltage divider 12 includes a plurality of resistors for dividing avoltage difference between a reference voltage VBB_high and the internalvoltage VBB. The first inverter I1 receives the reference voltageVBB_high and a power supply voltage VSS as a driving voltage and invertsan output of the voltage divider 12. The second inverter I2 receives thereference voltage VBB_high and the power supply voltage VSS as a drivingvoltage in order to generate a second output voltage B by inverting afirst output voltage A generated by the first inverter I1. Herein, thepower supply voltage VSS is a ground voltage.

The differential amplifier 14 amplifies a voltage difference between thefirst output voltage A and the second output voltage B. The thirdinverter I3 receives the reference voltage VBB_high and the power supplyvoltage VSS as a driving voltage in order to generate the detectionsignal BBE by inverting an output of the differential amplifier 14.

When the voltage level of the internal voltage VBB is higher than thatof the reference voltage VBB_high, the first output voltage A has avoltage level of the power supply voltage VSS and the second outputvoltage B has a voltage level of the reference voltage VBB_high.Therefore, the output of the differential amplifier 14 has a voltagelevel of the power supply voltage VSS. Accordingly, the detection signalBBE generated by the third inverter I3 is in a logic high level, i.e.,has a voltage level of the external power supply voltage VDD.

On the contrary, when the voltage level of the internal voltage VBB ismaintained as the voltage level of the reference voltage VBB_high, thefirst output voltage A has the voltage level of the reference voltageVBB_high and the second output voltage B has the voltage level of thepower supply voltage VSS. Accordingly, the output of the differentialamplifier 14 is in a logic high level and the detection signal BBE is ina logic low level.

FIG. 3 is a schematic circuit diagram showing the oscillator 20 shown inFIG. 1.

As shown, the oscillator 20 includes a first inverter chain 22 forgenerating a feed-backed periodic signal by delaying and inverting theperiodic signal OSC; a NAND gate ND1 for performing a logic NANDoperation to the feed-backed period signal and the detection signal; anda second inverter chain 24 for generating the periodic signal OSC bydelaying and inverting an output of the NAND gate ND1.

The oscillator 20 generates the periodic signal OSC according to thedetection signal BBE. That is, when the detection signal BBE is in alogic high level, the oscillator 20 generates the periodic signal OSC sothat the periodic signal OSC toggles having a predetermined period. Onthe contrary, when the detection signal BBE is in a logic low level, theperiodic signal OSC is in a logic low level.

FIG. 4A is a schematic circuit diagram illustrating the pumping controlsignal generator 30 shown in FIG. 1.

As shown, the pumping control signal generator 30 includes a first to athird delay units 32 to 36 and a signal generation unit 38.

The first delay unit 32 delays the periodic signal OSC to therebygenerate a first delayed-periodic signal T1. The second delay unit 34delays the first delayed-periodic signal T1 to thereby generate a seconddelayed-periodic signal T2. Similarly, the third delay unit 36 delaysthe second delayed-periodic signal T2 to thereby generate a thirddelayed-periodic signal T3.

The signal generation unit 38 receives the first to the thirddelayed-periodic signals T1 to T3 in order to generate a plurality ofpumping control signals, i.e., P1, P2, G1 and G2.

FIG. 4B is a wave diagram showing an operation of the pumping controlsignal generator 30 shown in FIG. 4A.

As shown, the pumping control signal P2 is a delayed version of theperiodic signal OSC and the pumping control signal P1 has an oppositephase in comparison with a phase of the pumping control signal P2. Anactivation period of the pumping control signal G1 includes anactivation period of the pumping control signal P2 and there is a90-degree phase difference between the pumping control signals G1 andG2.

Herein, it is assumed that the internal voltage VBB is higher than thereference voltage VBB_high, whereby the oscillator 20 generates theperiodic signal OSC and the level detector 10 activates the detectionsignal BBE as a logic high level.

FIG. 5 is a schematic circuit diagram depicting the charge pumping unit40 shown in FIG. 1.

As shown, the charge pumping unit 40 includes a first to a fourthcapacitors C1 to C4, a first and a second n-type metal oxidesemiconductor (NMOS) transistors NM1 and NM2, and a first to a sixthp-type metal oxide semiconductor (PMOS) transistors PM1 to PM6.

In detail, one terminal of the first capacitor C1 receives the pumpingcontrol signal P1 and the other terminal of the first capacitor C1 iscoupled to a node P1_BT. Similarly, one terminal of the third capacitorC3 receives the pumping control signal P2 and the other terminal of thethird capacitor C3 is coupled to a node P2_BT. A drain-source path ofthe second NMOS transistor NM2 is connected between the internal voltageVBB and the node P2_BT and a gate of the second NMOS transistor NM2 iscoupled to the node P1_BT. Similarly, a drain-source path of the firstNMOS transistor NM1 is connected between the internal voltage VBB andthe node P1_BT and a gate of the first NMOS transistor NM1 is coupled tothe node P2_BT.

One terminal of the second capacitor C2 receives the pumping controlsignal G1 and the other terminal of the second capacitor C2 is connectedto a node G1_BT. Similarly, one terminal of the fourth capacitor C4receives the pumping control signal G2 and the other terminal of thefourth capacitor C4 is coupled to a node G2_BT.

A source-drain path of the first PMOS transistor PM1 is connectedbetween the node P1_BT and the power supply voltage VSS and a gate ofthe first PMOS transistor PM1 is coupled to the node G1_BT. Asource-drain path of the fourth PMOS transistor PM4 is connected betweenthe node P2_BT and the power supply voltage VSS and a gate of the fourthPMOS transistor PM4 is coupled to the node G2_BT.

A source of the second PMOS transistor PM2 is coupled to the node G1_BTand a drain and a gate of the second PMOS transistor PM2 are coupled toa drain of the first PMOS transistor PM1. A source and a gate of thethird PMOS transistor PM3 are coupled to the node G1_BT and a drain ofthe third PMOS transistor PM3 is connected to the drain of the firstPMOS transistor PM1. A source of the sixth PMOS transistor PM6 iscoupled to the node G2_BT and a gate and a drain of the sixth PMOStransistor PM6 are coupled to a drain of the fourth PMOS transistor PM4.A source and a gate of the fifth PMOS transistor PM5 are coupled to thenode G2_BT and a drain of the fifth PMOS transistor PM5 is connected tothe drain of the fourth PMOS transistor PM4.

Referring to FIGS. 4B and 5, an operation of the charge pumping unit 40is described below. Herein, it is assumed that a point of time is ‘P’.

As shown in FIG. 4B, the pumping control signal P1 is in a logic highlevel, the pumping control signal G1 is in a logic low level and thepumping control signal G2 is in a logic high level. Therefore, accordingto the pumping control signal G1, the node G1_BT has a voltage level ofthe power supply voltage VSS. Accordingly, the first PMOS transistor PM1is turned on and, thus, the node P1_BT has a voltage level of the powersupply voltage VSS.

Meanwhile, according to the pumping control signal G2, the node G2_BThas a voltage level of the external power supply voltage VDD.Thereafter, the pumping control signal G1 transits to a logic high leveland the node G1_BT is increased to a voltage level of the external powersupply voltage VDD. Accordingly, the first PMOS transistor PM1 is turnedoff and, thus, the node P1_BT is disconnected from the power supplyvoltage VSS.

Thereafter, the pumping control signal P1 transits to a logic low leveland, thus, the node P1_BT has a voltage level of −VDD due to the firstcapacitor C1. Similarly, since the pumping control signal P2 transits toa logic high level, the node P2_BT has a voltage level of the externalpower supply voltage VDD due to the third capacitor C3.

Therefore, since a gate of the first NMOS transistor NM1 is coupled tothe node P2_BT, the first NMOS transistor NM1 is turned on so that thevoltage of −VDD loaded on the node P2_BT is outputted as the internalvoltage VBB.

Thereafter, a logic level of the pumping control signal G2 is changed toa logic low level and, thus, the node P2_BT is precharged to a voltagelevel of the power supply voltage VSS by the fourth PMOS transistor PM4.Then, the pumping control signal G2 transits to a logic high level.Therefore, the fourth PMOS transistor PM4 is turned off and the nodeP2_BT is disconnected from the power supply voltage VSS.

Thereafter, the pumping control signal P1 transits to a logic high leveland, thus, a voltage loaded on the node P1_BT is increased to a voltagelevel of the external power supply voltage VDD. Meanwhile, a voltageloaded on node P2_BT is decreased to a voltage level of −VDD as thepumping control signal P2 transits to a logic low level.

Accordingly, since the second NMOS transistor NM2 is turned on, avoltage level of −VDD loaded on the node P2_BT is outputted as theinternal voltage VBB.

Recently, a voltage level of an external power supply voltage iscontinuously decreased and it is required that an internal voltage has alower voltage level than −VDD. However, the conventional internalvoltage generator cannot generate an internal voltage whose voltagelevel is lower than −VDD.

In addition, as the pumping operation is performed, each voltage levelloaded on the nodes P1_BT and P2_BT is decreased. Accordingly, a pumpedvoltage cannot be efficiently outputted as the internal voltage.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide aninternal voltage generator for generating an internal voltage having alower voltage level.

In accordance with an aspect of the present invention, there is providedan internal voltage generator including: a latch unit for outputting afirst and a second driving signals based on a periodic signal; a firstpump block for generating the internal voltage in response to the firstdriving signal; and a second pump block for generating the internalvoltage in response to the second driving signal.

In accordance with another aspect of the present invention, there isprovided an internal voltage generator, including: a charge pumpingunit, the charge pumping unit including a first charging unit forcharging a first node and a second node to a different voltage level inresponse to an activation of a first pumping control signal; a firstpumping unit for performing a pumping operation to the first node inresponse to a second pumping control signal activated when the firstpumping control signal is inactivated; a second charging unit forcharging a third node and a fourth node to a different voltage level inresponse to an activation of a third pumping control signal; and asecond pumping unit for performing a pumping operation to the fourthnode in response to a voltage loaded on the second node, wherein avoltage loaded on the third node is outputted as an output controlsignal and a voltage loaded on the fourth node is outputted as aninternal voltage whose voltage level is negative; and a driving controlunit for generating the first to the third pumping control signals inresponse to a driving signal, wherein the first and the second pumpingcontrol signals have same phase and a phase of the third pumping controlsignal is opposite to a phase of the first pumping control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention willbecome apparent from the following description of preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing a conventional internal voltagegenerator;

FIG. 2 is a schematic circuit diagram depicting a level detector shownin FIG. 1;

FIG. 3 is a schematic circuit diagram showing an oscillator shown inFIG. 1;

FIG. 4A is a schematic circuit diagram illustrating a pumping controlsignal generator shown in FIG. 1;

FIG. 4B is a wave diagram showing an operation of the pumping controlsignal generator shown in FIG. 4A;

FIG. 5 is a schematic circuit diagram depicting a charge pumping unitshown in FIG. 1;

FIG. 6 is a block diagram showing an internal voltage generator inaccordance with a preferred embodiment of the present invention;

FIG. 7 is a schematic circuit diagram depicting a latch unit shown inFIG. 6;

FIG. 8 is a schematic circuit diagram showing a first pumping controlsignal generator shown in FIG. 6;

FIG. 9 is a schematic circuit diagram showing a first charge pumpingunit shown in FIG. 6;

FIG. 10 is a schematic circuit diagram showing an output driver shown inFIG. 6; and

FIG. 11 is a wave diagram showing an operation of the internal voltagegenerator shown in FIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, an internal voltage generator in accordance with thepresent invention will be described in detail referring to theaccompanying drawings.

FIG. 6 is a block diagram showing an internal voltage generator inaccordance with a preferred embodiment of the present invention.

As shown, the internal voltage generator includes a level detector 100,an oscillator 200, a latch unit 300, a first pumping control signalgenerator 400, a second pumping control signal generator 450, a firstcharge pumping unit 500, a second charge pumping unit 550 and an outputdriver 600.

The first and the second charge pumping units 500 and 550 perform anegative charge pumping operation to an external power supply voltageVDD in order to generate a voltage whose voltage level is lower thanthat of the external power supply voltage VDD. An output voltage of thefirst charge pumping unit 500 and an output voltage of the second chargepumping unit 550 are outputted as an internal voltage VBB by turns bythe output driver 600 according to an output control signal.

The level detector 100 detects a voltage level of the internal voltageVBB to thereby generate a detection signal BBE. The oscillator 200generates a periodic signal OSC in response to the detection signal BBE.The latch unit 300 receives the detection signal BBE in order togenerate a first driving signal AA and a second driving signal BB.Herein, the first and the second driving signals AA and BB have oppositephase.

The first pumping control signal generator 400 generates a first to athird pumping control signals, i.e., CNT_A1, CNT_A2 and BT_A0, inresponse to the first driving signal AA. The second pumping controlsignal generator 450 generates a fourth to a sixth pumping controlsignals, i.e., CNT_B1, CNT_B2 and BT_B0, in response to the seconddriving signal BB.

Since the first and the second driving signals AA and BB have oppositephase, an operation period of the first charge pumping unit 500 dose notoverlap with an operation period of the second charge pumping unit 550.

Meanwhile, the level detector 100, the oscillator 200, the latch unit300, the first pumping control signal generator 400 and the secondpumping control signal generator 450 constitute a driving control blockfor driving the first and the second charge pumping units 500 and 550based on a voltage level of the external power supply voltage VDD.

FIG. 7 is a schematic circuit diagram depicting the latch unit 300 shownin FIG. 6.

As shown, the latch unit 300 includes a first inverter I4 for generatingan inverted periodic signal OSCB by inverting the periodic signal OSC; afirst NOR gate NR1 and a second NOR gate NR2 cross-coupled forrespectively receiving the periodic signal OSC and the inverted periodicsignal OSCB; a second inverter I5 for generating the first drivingsignal AA by inverting an output of the first NOR gate NR1; and a thirdinverter I6 for generating the second driving signal BB by inverting anoutput of the second NOR gate NR2.

When the periodic signal OSC is in a logic high level, the first and thesecond driving signals AA and BB are in a logic high level and a logiclow level respectively. On the contrary, when the period signal OSC isin a logic low level, the first and the second driving signals AA and BBare in a logic low level and a logic high level respectively. Herein,since the first and the second driving signals AA and BB are generate bythe cross-coupled NOR gates, i.e., the first and the second NOR gatesNR1 and NR2, the first and the second driving signals AA and BB have180-degree phase difference regardless of variations due to amanufacturing process.

FIG. 8 is a schematic circuit diagram showing the first pumping controlsignal generator 400 shown in FIG. 6.

As shown, the first pumping control signal generator 400 includes afirst buffer 420 for generating the second pumping control signal CNT_A2by buffering the first driving signal AA; a second buffer 440 forgenerating the first pumping control signal CNT_A1 by buffering thefirst driving signal AA; and a fourth inverter I7 for generating thethird pumping control signal BT_A0 by inverting an output of the secondbuffer 440.

When the first driving signal AA is in a logic high level, the firstpumping control signal generator 400 outputs the first and the secondpumping control signals CNT_A1 and CNT_A2 as a logic high level andoutputs the third pumping control signal BT_A0 as a logic low level. Onthe other hand, when the first driving signal AA is in a logic lowlevel, the first and the second pumping control signals CNT_A1 andCNT_A2 are in a logic low level and the third pumping control signalBT_A0 is in a logic high level.

Herein, since a structure and an operation of the second pumping controlsignal generator 450 are same to those of the first pumping controlsignal generator 400, detailed descriptions of the second pumpingcontrol signal generator 450 are omitted.

FIG. 9 is a schematic circuit diagram showing the first charge pumpingunit 500 shown in FIG. 6.

As shown, the first charge pumping unit 500 includes a first chargingunit 520 for charging a first node BT_A1 and a second node BT_A2 inresponse to an activation of the first pumping control signal CNT_A1 sothat the first and the second nodes BT_A1 and BT_A2 have a differentvoltage level; a first pumping unit C5 for performing a pumpingoperation to the first node BT_A1 in response to the third pumpingcontrol signal BT_A0 activated when the first pumping control signalCNT_A1 is inactivated; a second charging unit 540 for charge a thirdnode BT_A3 and a fourth node TR_A0 in response to an activation of thesecond pumping control signal CNT_A2 so that the third and the fourthnodes BT_A3 and TR_A0 have a different voltage level; and a secondpumping unit C6 for performing a pumping operation to the third nodeBT_A3 in response to a voltage loaded on the second node BT_A2. Thefirst charge pumping unit 500 outputs a voltage loaded on the fourthnode TR_A0 as an output control signal and outputs a voltage loaded onthe third node BT_A3 as an output voltage.

In detail, the first charging unit 520 includes a first n-type metaloxide semiconductor (NMOS) transistor NM3, a second NMOS transistor NM4and a second p-type metal oxide semiconductor (PMOS) transistor PM8.

A source-drain path of the second PMOS transistor PM8 is connectedbetween the external power supply voltage VDD and the second node BT_A2and a gate of the second PMOS transistor PM8 receives the first pumpingcontrol signal CNT_A1. A drain-source path of the first NMOS transistorNM3 is connected between the second node BT_A2 and the first node BT_A1and a gate of the first NMOS transistor NM3 receives the first pumpingcontrol signal CNT_A1. A drain-source path of the second NMOS transistorNM4 is connected between the first node BT_A1 and a power supply voltageVSS and a gate of the second NMOS transistor NM4 is coupled to thesecond node BT_A2.

The second charging unit 540 includes a third NMOS transistor NM5, afourth NMOS transistor NM6 and a first PMOS transistor PM7.

A sour-drain path of the first PMOS transistor PM7 is connected betweenthe power supply voltage VDD and the fourth node TR_A0 and a gate of thefirst PMOS transistor PM7 receives the second pumping control signalCNT_A2. A drain-source path of the third NMOS transistor NM5 isconnected between the fourth node TR_A0 and the third node BT_A3 and agate of the third NMOS transistor NM5 receives the second pumpingcontrol signal CNT_A2. A drain-source path of the fourth NMOS transistorNM6 is connected between the third node BT_A3 and the power supplyvoltage VSS and a gate of the fourth NMOS transistor NM6 is coupled tothe fourth node TR_A0.

The first pumping unit C5 includes a capacitor whose one terminal andthe other terminal are respectively coupled to the third pumping controlsignal BT_A0 and the first node BT_A1. Similarly, the second pumpingunit C6 includes a capacitor connected between the second node BT_A2 andthe third node BT_A3.

FIG. 10 is a schematic circuit diagram showing the output driver 600shown in FIG. 6.

As shown, the output driver 600 includes a fifth NMOS transistor NM7 foroutputting an output voltage BT_A3 of the first charge pumping unit 500as the internal voltage VBB in response to an output control signalTR_B0 of the second charge pumping unit 550; and a sixth NMOS transistorNM8 for outputting an output voltage BT_B3 of the second charge pumpingunit 550 as the internal voltage VBB in response to an output controlsignal TR_A0 of the first charge pumping unit 500.

FIG. 11 is a wave diagram showing an operation of the internal voltagegenerator shown in FIG. 6.

Referring to FIGS. 6 to 11, the operation of the internal voltagegenerator is described below.

Herein, it is assumed that the internal voltage VBB is higher than areference voltage VREF_high so that the detection signal BBE isactivated and the oscillator 200 constantly generates the periodicsignal OSC. The description of the operation of the internal voltagegenerator begins at the timing ‘P’.

In response to an activation of the periodic signal OSC, the latch unit300 outputs the first driving signal AA and the second driving signal BBas a logic high level and a logic low level respectively. At this time,the first pumping control signal generator 400 outputs the first and thesecond pumping control signals CNT_A1 and CNT_A2 as a logic low level inresponse to the first driving signal AA.

Therefore, the second node BT_A2 and the fourth node TR_A0 areprecharged to a voltage level of the external power supply voltage VDDby the second PMOS transistor PM8 and the first PMOS transistor PM7respectively. Also, the first node BT_A1 and the third node BT_A3 areprecharged to a voltage level of the power supply voltage VSS.

Thereafter, since the first and the second pumping control signalsCNT_A1 and CNT_A2 transits to a logic high level, the first and thesecond PMOS transistors PM7 and PM8 are turned off and the first NMOStransistor NM3 and the third NMOS transistor NM5 are turned on.Therefore, the second node BT_A2 and the fourth node TR_A0 aredisconnected from the external power supply voltage VDD. Also, since thesecond and the fourth NMOS transistors NM4 and NM6 are turned off due tovoltages loaded on the second node BT_A2 and the fourth node TR_A0, thefirst and the third nodes BT_A1 and BT_A3 are disconnected from thepower supply voltage VSS.

Meanwhile, since the third pumping control signal BT_A0 transits to alogic low level, the first node BT_A1 has a voltage level of −VDD andthe second node BT_A2 also has a voltage level of −VDD due to the turnedon first NMOS transistor NM3. Therefore, a voltage loaded on the thirdnode BT_A3 is decreased to a voltage level of −2VDD due to a negativepumping operation performed by the second pumping unit C6 whose oneterminal is coupled to the second node BT_A2. Also, the fourth nodeTR_A0 has a voltage level of −2VDD due to the turned on third NMOStransistor NM5.

Herein, although not shown, since the fourth to the sixth pumpingcontrol signals, i.e., CNT_B1, CNT_BT and BT_B0, have an opposite phasein comparison with the first to the third pumping control signals CNT_A1to BT_A0, the output voltage BT_B3 and the output control signal TR_B0generated by the second charge pumping unit 550 have a voltage level ofthe external power supply voltage VDD.

Therefore, the sixth NMOS transistor NM8 is turned off by the outputcontrol signal TR_A0 of the first charge pumping unit 500 and the fifthNMOS transistor NM7 is turned on by the output control signal TR_B0 ofthe second charge pumping unit 550. Since the fifth NMOS transistor NM7is turned on, a voltage loaded on the third node BT_A3 of the firstcharge pumping unit 500 is outputted as the internal voltage VBB.

Meanwhile, at a next half period of the oscillator 200, the first chargepumping unit 500 does not perform a negative pumping operation.Accordingly, the output voltage BT_A3 and the output control signalTR_A0 have a voltage level of the external power supply voltage VDD, andthe second charge pumping unit 550 outputs the output voltage BT_B3 andthe output control signal TR_B0 as a voltage level of −2VDD byperforming a negative pumping operation to the external power supplyvoltage VDD.

Then, the output driver 600 outputs a voltage loaded on a node BT_B3 ofthe second charge pumping unit 550 as the internal voltage VBB throughthe sixth NMOS transistor NM8 turned on by the output control signalTR_A0 generated by the first charge pumping unit 500.

As above-mentioned, since the driving control signals, i.e., AA and BB,are generated having 180-degree phase difference, it is prevented thatdriving periods of the first and the second charge pumping units areoverlapped each other or no output is generated. Accordingly, aninternal voltage can hold a stable voltage level.

Also, while the conventional internal voltage generator cannot generatean internal voltage lower than −VDD, the internal voltage generator inaccordance with the present invention generates an internal voltagehaving a voltage level of −2VDD. Therefore, it is possible to generate arequired internal voltage level even though a voltage level of anexternal power supply voltage is decreased.

Further, according to the conventional internal voltage generator, avoltage level required to turn on an output driver is increased as apumping operation is performed. However, since the internal voltagegenerator generates not only an output voltage but also an outputcontrol signal by performing a pumping operation to an external powersupply voltage, such a problem can be solved.

The present application contains subject matter related to Korean patentapplication No. 2005-36267, filed in the Korean Patent Office on Apr.29, 2005, the entire contents of which being incorporated herein byreference.

While the present invention has been described with respect to theparticular embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1-13. (canceled)
 14. An internal voltage generator, comprising: a charge pumping means, the charge pumping means including a first charging unit for charging a first node and a second node to a different voltage level in response to an activation of a first pumping control signal; a first pumping unit for performing a pumping operation to the first node in response to a second pumping control signal activated when the first pumping control signal is inactivated; a second charging unit for charging a third node and a fourth node to a different voltage level in response to an activation of a third pumping control signal; and a second pumping unit for performing a pumping operation to the fourth node in response to a voltage loaded on the second node, wherein a voltage loaded on the third node is outputted as an output control signal and a voltage loaded on the fourth node is outputted as an internal voltage whose voltage level is negative; and a driving control means for generating the first to the third pumping control signals in response to a driving signal, wherein the first and the second pumping control signals have same phase and a phase of the third pumping control signal is opposite to a phase of the first pumping control signal.
 15. The internal voltage generator as recited in claim 14, wherein the first charging unit includes: a first PMOS transistor whose source-drain path is connected between the external power supply voltage and the second node, wherein a gate of the first PMOS transistor receives the first pumping control signal; a first NMOS transistor whose drain-source path is connected between the second node and the first node, wherein a gate of the first NMOS transistor receives the first pumping control signal; and a second NMOS transistor whose drain-source path is connected between the first node and a power supply voltage, wherein a gate of the second NMOS transistor is coupled to the second node.
 16. The internal voltage generator as recited in claim 14, wherein the second charging unit includes: a second PMOS transistor whose source-drain path is connected between the external power supply voltage and the third node, wherein a gate of the second PMOS transistor receives the second pumping control signal; a third NMOS transistor whose drain-source path is connected between the third node and the fourth node, wherein a gate of the third NMOS transistor receives the second pumping control signal; and a fourth NMOS transistor whose drain-source path is connected between the fourth node and the power supply voltage, wherein a gate of the fourth NMOS transistor is coupled to the third node.
 17. The internal voltage generator as recited in claim 16, wherein the first pumping unit includes a first capacitor whose one terminal receives the second pumping control signal and the other terminal is coupled to the first node and the second pumping unit includes a second capacitor connected between the second node and the fourth node. 